In synchronous digital circuits, a data input must settle and hold its value for a specific window before the clock transition arrives. If the signal changes during this critical window, the flip-flop might capture the wrong state or enter a metastable condition. Designers balance this timing constraint against propagation delays to ensure reliable data capture at high clock speeds.
We're violating setup time on the main data bus, so drop the clock frequency down to 100 megahertz and see if it boots.
Setup time violations are usually fixed by slowing down the clock or reducing the logic depth between registers.
Related terms
Clock
A continuous square wave signal that synchronizes the timing of digital circuits.
Clock skew
The time difference between a clock signal arriving at different parts of a circuit.
Edge-triggered
A digital input that responds only to the transition of a clock signal.
Flip-flop
A bistable logic circuit that stores a single bit of binary data.
Propagation delay
The time it takes for a logic signal to travel through a gate and change its output state.