An edge-triggered circuit, like a flip-flop, captures its input data exactly at the moment a clock signal transitions from low to high or high to low. It ignores the input state during the steady high or low periods of the clock. This precise timing prevents race conditions in synchronous logic designs, ensuring data moves through a pipeline exactly one stage per clock cycle.
Heard on the job
Make sure that flip-flop is positive edge-triggered so it samples data after the bus settles.
Insider tip
Mixing positive and negative edge-triggered logic in the same clock domain is a classic way to halve your timing budget and cause routing headaches.
Do not mix it up with
- Level-triggered: Edge-triggered devices respond to the moment of transition, while level-triggered devices remain transparent as long as the clock signal is held high or low.