In a single data rate system, components sample or transmit information exclusively during one transition of the clock pulse, such as the upward or downward shift. This serves as a straightforward method for synchronizing digital parts. By utilizing just one transition per cycle, it yields exactly half the theoretical bandwidth of a double data rate system running at an identical clock frequency.
The peripheral bus uses single data rate, so we only need to sample it during the upward shift.
Also heard as
- SDR
Related terms
DDR
Double data rate is a clocking technique that transfers data on both the rising and falling edges of a clock signal.
Clock
A continuous square wave signal that synchronizes the timing of digital circuits.
Positive-edge-triggered
Describing a digital component that only changes state when its clock signal transitions from low to high.
Edge-triggered
A digital input that responds only to the transition of a clock signal.