Double data rate (DDR) is a bus signaling method that doubles the bandwidth of a digital link without increasing the clock frequency. It works by triggering data transfers on both the rising and falling edges of the clock pulse. Engineers use this technique heavily in memory interfaces and high-speed communication links to maximize throughput while keeping clock speeds manageable, which helps control electromagnetic interference and power consumption.
Make sure you match the trace lengths on the DDR bus so we don't get setup and hold violations on the falling edge.
Because DDR uses both clock edges, the duty cycle of the clock signal must be kept as close to 50 percent as possible to ensure symmetric timing margins.
Related terms
Clock
A continuous square wave signal that synchronizes the timing of digital circuits.
Edge-triggered
A digital input that responds only to the transition of a clock signal.
SDR
A memory or bus interface that transfers data once per clock cycle.
QDR
Quad data rate is a memory communication signaling method that transfers data on four points of the clock cycle.