Clock skew occurs when a single timing signal takes longer to reach some components than others, usually due to differences in trace lengths or capacitive loading on the printed circuit board. If the skew exceeds the setup or hold time of the receiving flip-flops, it causes data corruption. Designers use clock trees and matched trace lengths to minimize it.
The layout routing is causing massive clock skew between the processor and the RAM.
Also heard as
- Skew
Related terms
Clock
A continuous square wave signal that synchronizes the timing of digital circuits.
Setup time
The required duration a data signal must remain stable before a clock edge triggers.
Race condition
A logic failure where the output depends on the unpredictable timing of two or more competing signals.
Propagation delay
The time it takes for a logic signal to travel through a gate and change its output state.