A race condition occurs in digital logic and asynchronous circuits when multiple inputs change state nearly simultaneously, and the final output depends on which signal arrives first. If delays in the physical routing or gates cause the signals to arrive in an unintended order, the circuit can latch incorrect data or enter an invalid state. Designers prevent these timing hazards by using synchronous, clock-driven logic and carefully matching propagation delays.
Heard on the job
We're seeing random bit flips on the bus because there's a race condition between the write enable and the address lines.
Also heard as
- logic hazard