Ratioless logic is a circuit design technique where logic states are determined entirely by switches pulling the output to a supply rail or ground, rather than by a voltage divider formed by the resistance of competing transistors. Standard CMOS logic is inherently ratioless because the pull-up and pull-down networks are never fully conducting at the same time. This approach minimizes static power consumption and makes the circuit highly tolerant to manufacturing variations.
The new cell library uses purely ratioless logic to ensure reliable operation at lower supply voltages.
Related terms
CMOS
Complementary metal-oxide-semiconductor is the dominant fabrication technology for integrated circuits.
Logic level
A specific voltage range that represents a distinct binary state in a digital circuit.
nMOS
A type of field-effect transistor that uses negatively charged electrons as the primary charge carriers.