SerDes stands for serializer/deserializer. It takes wide, slow parallel data from a chip and funnels it into a fast, narrow serial link for transmission, then reverses the process at the receiving end. This architecture drastically reduces the number of pins and traces required on a circuit board, avoiding the clock skew issues inherent in wide parallel buses.
The new FPGA has thirty-two gigabit SerDes lanes available for backplane routing.
High-speed SerDes design is heavily dependent on analog techniques, requiring careful impedance matching and equalization to recover the clock from the data stream.
Related terms
PCIe
A high-speed serial computer expansion bus standard for connecting hardware devices.
FPGA
A field-programmable gate array is an integrated circuit whose internal logic can be configured by the user.
Clock skew
The time difference between a clock signal arriving at different parts of a circuit.
LVDS
A high-speed digital interface standard that uses low voltages and twisted wire pairs.