A delay-locked loop (DLL) compares the phase of an incoming clock signal with a reference clock and dynamically adjusts a chain of delay gates to align them. Unlike a phase-locked loop (PLL) which uses a voltage-controlled oscillator to generate a new frequency, a DLL only shifts the phase of the existing signal. They are heavily used in high-speed memory interfaces like DDR to eliminate clock skew.
The DDR interface needs the DLL enabled to keep the data lines aligned with the clock edges.
Also heard as
- delay-locked loop
Do not mix it up with
- PLL: A PLL changes frequency using an oscillator, whereas a DLL only changes phase by delaying the signal.
Related terms
PLL
A phase-locked loop circuit that synchronizes an output oscillator with a reference signal.
Clock skew
The time difference between a clock signal arriving at different parts of a circuit.
DDR
Double data rate is a clocking technique that transfers data on both the rising and falling edges of a clock signal.