A synchronization error in digital logic where a flip-flop or register captures data at the incorrect moment. This usually happens due to clock skew, jitter, or setup and hold violations. The result is corrupted data propagating through the pipeline, often leading to unpredictable system crashes or state machine lockups.
We're getting a misclock on the data bus because the trace length mismatch is eating into our setup time.
A misclock is notoriously hard to debug because it often looks like a random software bug, but it usually points to a physical layout issue or thermal drift.
Related terms
Clock skew
The time difference between a clock signal arriving at different parts of a circuit.
Race condition
A logic failure where the output depends on the unpredictable timing of two or more competing signals.
Setup time
The required duration a data signal must remain stable before a clock edge triggers.
Clock
A continuous square wave signal that synchronizes the timing of digital circuits.