Clock domain crossing occurs when data moves between parts of a chip operating at different clock frequencies or phases. If not handled correctly with synchronizers like dual-flop stages or asynchronous FIFOs, it causes metastability, where flip-flops settle into unpredictable states and corrupt data. Verifying these boundaries is a major step in ASIC and FPGA design.
Heard on the job
The linting tool flagged a CDC violation where the 100 megahertz bus talks to the PCIe controller.
Insider tip
A missing CDC synchronizer is the classic cause of a chip that simulates perfectly but fails randomly on the test bench.
Also heard as
- clock domain crossing