Unclocked circuits, also known as asynchronous logic, process signals as soon as inputs change rather than waiting for a clock edge. This approach eliminates clock skew and reduces power consumption since parts of the circuit only draw power when actively switching. However, designing them requires careful management of propagation delays to avoid race conditions.
We used an unclocked latch for the interrupt handler so it catches the pulse immediately.
Related terms
Clock
A continuous square wave signal that synchronizes the timing of digital circuits.
Clock skew
The time difference between a clock signal arriving at different parts of a circuit.
Race condition
A logic failure where the output depends on the unpredictable timing of two or more competing signals.
Combinational logic
A type of digital logic where outputs are determined entirely by the present combination of inputs.