A vernier delay line uses two parallel chains of delay elements with slightly different propagation times. By comparing the outputs of the two chains, the circuit can measure or generate time intervals much smaller than the delay of a single logic gate. This technique is heavily used in time-to-digital converters and high-speed memory interfaces.
Heard on the job
We need a VDL to calibrate the clock skew down to the picosecond range.
Also heard as
- vernier delay line